This invention relates to a manufacturing method for cascaded junction type field effect transistors (which are hereinafter referred to as cascade FETs), and more particularly to a method for manufacturing two junction gates of a cascade FET.
In general, a cascade FET is formed as shown in FIG. 1. N-type channel region 12 is formed on P+-type semiconductor substrate 11. N+-type source region 13 and drain region 14 are formed with a predetermined distance from each other in the surface of channel region 12. Further, first and second P+-type junction gates 15 and 16 are formed with a predetermined distance from each other in that surface area of channel region 12 which lies between source and drain regions 13 and 14. Insulation film 17 is formed on channel region 12. Contact holes 18 and 19 are formed in those portions of insulation film 17 which are positioned on source and drain regions 13 and 14. Source and drain regions 13 and 14 are respectively connected to source and drain electrodes 20 and 21 via contact holes 18 and 19. Contact holes 22 and 23 are formed in those portions of insulation film 17 which are positioned on junction gates 15 and 16. Junction gates 15 and 16 are respectively connected to gate electrodes 24 and 25 via contact holes 22 and 23. Source electrode 20 and gate electrode 25 connected to second junction gate 16 which is formed near drain region 14 are connected to semiconductor substrate 11.
FIG. 2 shows an equivalent circuit of the cascade FET of FIG. 1. First junction FET 26 is formed of substrate 11, channel region 12, source region 13, drain region 14 and first junction gate 15. Second junction FET 27 is formed of substrate 11, channel region 12, source region 13, drain region 14 and second junction gate 16. Thus, the cascade FET has first common source junction FET 26 and second gate common junction FET 27 which are cascade connected. Since two junction FETs 26 and 27 are thus cascade connected, a feedback capacitance component from the drain of junction FET 26 is substantially grounded with respect to A.C. signals and the FET has a small feedback capacitance Crss. That is, as is well known in the art, feedback capacitance Crss of the junction FET is represented by the sum of "Cj+Cm" in which Cj is a junction capacitance between the gate and drain and Cm is a MOS capacitance associated with the aluminum wiring section between the gate and drain. MOS capacitance Cm is extremely small in comparison with junction capacitance. In the cascade FET, junction capacitor Cj between the gate and drain of first junction FET 26 is grounded via second junction gate 16, and therefore junction capacitance Cj will be "0" in the high frequency operation mode. In this case, "Crss=Cm" is attained, and the cascade FET will have feedback capacitance Crss than that of a single FET.
Further, in the cascade FET described above, a voltage between the drain and source of first junction FET 26 becomes equal to that between the gate and source of second junction FET 27, and thus first junction FET 26 applies a negative bias to second junction FET 27. Thus, the general characteristic of the cascade FET depends on the combination of characteristics of junction FETs 26 and 27.
It is well known that, in the cascade FET, forward admittance .vertline.Yfs .vertline. and feedback capacitance Crss will change according to the ratio of pinch-off voltages V.sub.G1S(OFF) and V.sub.G2S(OFF) between the gate and source of junction FETs 26 and 27. Pinch-off voltages V.sub.G1S(OFF) and V.sub.G2S(OFF) between the gate and source are respectively determined by channel widths Wl and W2 and the impurity concentration of those portions of channel region 12 which lies under junction gates 15 and 16 of first and second FETs 26 and 27.
FIG. 3 shows the static characteristic of first FET 26 and the transfer characteristic of second FET 27. In the case where pinch-off voltage V.sub.G2S(OFF) between the gate and source of FET 27 is substantially equal to pinch-off voltage V.sub.G1S(OFF) between the gate and source of FET 26 as shown by solid line 28, forward transfer admittance .vertline.Yfs .vertline. is lowered in an operation region in which saturation drain current I.sub.DSS flows as shown by broken line 29 in FIG. 4. Therefore, in order to attain the normal characteristic forward transfer admittance .vertline.Yfs .vertline. (that is, forward transfer admittance .vertline.Yfs .vertline. is not lowered in an operation region in which saturation drain current I.sub.DSS flows) as shown by solid line 30 in FIG. 4, it becomes necessary to set pinch-off voltage V.sub.G2S(OFF) between the gate and source of FET 27 larger than twice pinch-off voltage V.sub.G1S(OFF) between the gate and source of FET 26 as shown by solid line 31 in FIG. 3.
It is also known that feedback capacitance Crss of the FET has a large value in the nonsaturation region, it is necessary to set voltage V.sub.DS between the source and drain so as to satisfy the condition that "V.sub.DS &gt;[V.sub.G1S(OFF) +V.sub.G2S(OFF) ]". Recently, a low drain voltage is often used, and therefore it is necessary to attain the characteristic of feedback capacitance Crss with respect to voltage V.sub.DS between the source and drain as shown in FIG. 5. In general, in order to attain drain-source voltage V.sub.DS of 5 V and low feedback capacitance Crss, it is necessary to satisfy the condition that V.sub.G2S(OFF) =5V.sub.G1S(OFF), and V.sub.G2S(OFF) &lt;V.sub.G1S(OFF).
Pinch-off voltages V.sub.G1S(OFF) and V.sub.G2S(OFF) between the gate and source of junction FETs 26 and 27 are determined by the impurity concentrations of junction gates 15, 16 and channel region 12 and widths Wl and W2. For forming junction gates 15 and 16, an impurity is first selectively diffused into an element formation region for junction gate 15 to form a P+-type region. Then, an impurity is diffused into element formation regions for first and second junction gates 15 and 16 while the reverse withstanding voltage of the P+-type region is being measured and the diffusion depth thereof is controlled, and thus junction gates 15 and 16 are formed. However, if junction gates 15 and 16 are formed in two diffusion steps, the ratio V.sub.G1S(OFF) /V.sub.G2S(OFF) of pinch-off voltages between the gate and source may vary in the same production lot and between different production lots.
FIG. 6 shows variations in the ratio V.sub.G2S(OFF) /V.sub.G1S(OFF) of pinch-off voltages between the gate and source in the same lot and between different lots in the case where junction gates 15 and 16 are formed by performing two diffusion steps. As shown in FIG. 6, variation is caused in the ratio of the same lot and greater variation is caused in the ratios between different lots.
Therefore, feedback capacitance Crss and forward transfer admittance .vertline.Yfs .vertline. are affected to easily vary, lowering the manufacturing yield. Variation in the ratio V.sub.G2S(OFF) /V.sub.G1S(OFF) of pinch-off voltages between the gate and source is directly caused by variation in the ratio W2/Wl of the channel widths and impurity concentration of the diffusion layers of junction gates 15 and 16. Further, it is affected by the impurity concentration and diffusion depth of the diffusion layer formed in the first diffusion step for forming junction gate 15. In the diffusion step effected to control saturation drain current I.sub.DSS, since diffusion speed of junction gate 15 is different from that of junction gate 16, it becomes difficult to precisely set the channel width ratio W2/Wl.